This paper presents a new pulse width modulation (PWM) strategy, called extended double carrier PWM, for a two-level voltage source inverter aiming at reducing the RMS current flowing through dc link filtering capacitors on embedded systems over a large modulation index range and for high-power factor loads (cos φ ≥ 0.8). Instead of utilizing two adjacent active vectors at each switching period as in classic PWM strategies, this new strategy utilizes two nonadjacent active vectors in the case of low-modulation index or three consecutive active vectors in the case of high-modulation index. Analytical calculations show that this new strategy is particularly effective in terms of reducing filtering capacitor rms current for high-power factor compared to space vector PWM which is used as a reference strategy. The impact of this strategy on output current quality is also investigated.